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In the following chapters we will explain the further instructions of VHDL but always on simple examples.

Content

 
 Hardware FPGA and ASIC

 Introduction
 Different digital integrated circuits
 ASIC and ASSP
 FPGA
 Logic blocks and sampling clock
 Different memory and logic blocks
 Parallel versus sequential
 Algorithm, VHDL and implementation
 FPGA maker

 The first VHDL example

 Introduction
 Start new project (Example 10)
 Entity
 Port
 Architecture
 AND-function
 Testbench
 Componente
 Signals
 Instance and process
 Assign sequential values
 Simulation (Example_10)
 VHDL can also mathematical calculation (Example_15)
 By position and by name assignment
 Synthesis

 VHDL Instruction

 Introduction
 Assert (Example_20)
 Two AND-blocks
 Behavioural description (Example_30)
 Structural description (Example_35)
 Functional and structural description
 Consumption time (Example_40)
 AFTER and TRANSPORT
 Generic_(Example_45)
 Array and Record (Example_50)
 Data types
 Integer
 Operators
 SUBTYPE and TYPE
 Multiplexer 4to1
 Multiplexer 4to1
 Result of the synthesis tool
 The synthesis result in SPICE (Example_55)
 Simulation (Example_55)
 Multiplexer 4to1 for 8Bit signals

 Concurrency vs. sequential

 Introduction
 Several processes
 Process => sequential execution
 AND-process without sensitivity list (Example_90)
 AND-process with sensitivity list (Example_100)
 Concurrent processes (Example_110)
 Example with variables (Example_110)
 Signals and variables
 Signal assignment two times
 Signal assignment two times
 Control instruction
 Conditional assignment in the concurrent world

 Asynchron and synchron

 Introduction
 Advantage and disadvantage
 D-Flip-Flop_(Example_120)
 Synchron on rising edge (Example_130)
 Synchron on positive edge and reset (Example_140)
 4 Bit Shift-Register
 4 Bit Shift-Register in VHDL_(Example_150)
 How long has to be the CLK period?

 Automats

 Introduction
 Principle of the State-Machine
 Graphical presentation of the state and transition
 Automat in VHDL (Example_200)
 New data type and signals declaration (Example_200)
 State-memory block
 Next state
 Output logic block
 The total architecture
 Testbench
 Simulation
 RESET
 CLK-generator
 Not only High and Low!

 Bus systems

 Introduction
 Why Tri-State?
 The package std_logic_1164
 Tri-State in VHDL
 Transceiver
 Transceiver
 Transceiver simulation (Example_260)
 Read from the bus line (Example_270)
 Bus system
 Two transceiver on the same line

 ENDE